1. Field of the Invention
The present invention relates to a technique for transmitting a clock signal.
2. Description of the Background Art
In designing an integrated circuit having a plurality of modes of operating frequencies, the assumed maximum operating frequency may be such that it is at an acceptable level for putting the integrated circuit into operation. In the integrated circuit, a demand for high speed operation grows as a frequency of a clock signal, depending on which the integrated circuit operates, becomes higher. The result is an increase in power consumption of the integrated circuit. Accordingly, when the frequency of a clock signal provided to the integrated circuit is low, though the configuration of the integrated circuit is responsive to high speed operation, an unnecessarily large amount of power may be consumed.
In light of this, a technique for transmitting a clock signal using a plurality of buffers has been suggested, as disclosed in Japanese Patent Application Laid-Open No. 10-209284 (1998), for example. According to this technique, the plurality of buffers are selectively put into operation on the basis of a frequency of a clock signal applied thereto.
In response to the case of transmission of a clock signal having a high frequency, an interconnect line for carrying a clock signal (hereinafter referred to as a “clock transmission line”) has a large linewidth for reduction in line resistance. In order for the transmission line to resist crosstalk noise from another interconnect line, it is preferable to independently provide a shielding line around the transmission line, and to apply a fixed potential to this shielding line.
On the other hand, for reduction in power consumption, a driving capability of a buffer which operates in response to a low-frequency clock signal is kept low. Due to this, when a low-frequency clock signal is provided from this buffer to the transmission line, an unnecessary increase in line capacitance is caused, leading to wasted power consumption.